1. Field of the Invention
The present invention relates to a structure and process for forming polysilicon resistors on semiconductor substrates, and more particularly to dual layer polysilicon high value resistor structures.
2. Background Information
Forming high value polysilicon resistors on the same wafer together with other circuit components can be difficult. One reason is that the thickness of the polysilicon layer or layers is determined by the required characteristics of the other devices. For example, the deposited polysilicon must also form the gates and/or emitters of active components, lower value resistors and capacitor plates. This requires thicknesses that are typically greater than 200 nanometers (nm).
As illustrated in FIG. 1, polysilicon resistivity is a non-linear function of doping where the resistivity decreases quickly as the doping concentration increases. Implant dopant concentration control makes resistivity greater than about 0.060 ohm-cm difficult to achieve. Since, as the doping concentration is reduced (compare point a to point b in FIG. 1), the rate of change of resistivity with doping concentrations increases dramatically making control of resistivity and thus resistance difficult. These two restrictions limit practical sheet resistances to not much above 2000 ohms/square. Therefore, mega-ohm resistors will consume much space and will greatly increase die size.
Attempts to form high value polysilicon resistors have used ion implants and reduced polysilicon thicknesses with limited success. Other structures have used multiple layers of polysilicon. But, these often require many additional steps and processes beyond those needed for the core devices on the same wafer, and the resulting resistors have device and process control limitations.
One such attempt is described in U.S. Pat. No. 6,211,031 to Dah-Chih Lin et al. This invention describes a split or dual value polysilicon process using two layers. A first layer is deposited and patterned to expose the underlying dielectric substrate. A second polysilicon layer is deposited over the first layer and the dielectric. Dual parallel resistors are formed. If the polysilicon resistivity is too high, the resistor end contact structures will form rectifying contacts. There is no suggestion or disclosure of processing to provide low ohmic end structures. The process of etching a contact hole that terminates on but does not go through the thin poly layer is also difficult.
Another approach is found in U.S. Pat. No. 6,054,359 to Yu-Ming Tsui et al. This patent describes a thin polysilicon layer with a thicker polysilicon layer overlaying the thinner layer. The thin layer is doped in place and the thicker layer is undoped. The combination of the two layers forms the resistor. This particular invention suffers especially from the undoped layer forming part of the end structures of the resistors being formed. The result is relatively high ohmic end contacts for the resistors.
Prior art does not address the technical problems of integrating silicide or metal contacts into thin polysilicon resistors. In the case of silicide, the forming reaction will consume much if not all of a thin, poly layer. For contact etch, the required over-reach can completely burrow through the poly. Each of the above can make the resistor non-functional or unreliable. For these reasons, prior art techniques, often are forced to accept high impedance end structures or even non-ohmic connections.
Therefore, a need remains to provide high value polysilicon integrated circuit resistors having existing process compatibility; with few, if any, added process steps; and with well controlled resistor end structures having relatively low ohmic resistances to the metalization layer.